Reducing Cache Conflicts by Multi-Level Cache Partitioning and Array Elements Mapping

• Main Authors: Hsi-Chiuen Chen, 陳熙君
• Other Authors: Jang-Ping Sheu
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/57932239567867333952

碩士 === 國立中央大學 === 資訊工程研究所 === 87 === This paper presents an algorithm to reduce cache conflicts and improve cache localities. The proposed algorithm analyzes the reference pattern of innermost loop, partitions the multi-level cache into several parts with different size, and then maps array data onto the scheduled cache positions such that cache conflicts can be eliminated. To reduce the memory overhead for mapping arrays onto partitioned cache, methods for array redeclaration and program transformation are also developed. Besides, we combine the loop tiling and the proposed schemes to improve the cache performance for those programs that the amount of accessing elements of innermost loop is larger than cache partitioned size. The developed scheme can be applied to arbitrary loops programs whose array accessing functions are affine. To demonstrate that our approach is effective at reducing number of cache conflicts and exploiting cache localities, we use Atom as tool to simulate the behavior of direct-mapped cache. Experimental results show that applying our cache partition scheme can largely reduce the cache conflicts and thus save program execution time in both one-level cache and multi-level cache hierarchies.