| Summary: | 碩士 === 國立交通大學 === 電機與控制工程系 === 87 === Speech communication is at present the most dominant and common service in telecommunication. Digital transmission of speech is more versatile, providing the opportunity of achieving costs, consistent quality, security and spectral efficiency in the systems that exploit it. Due to the increase in number of users and limited bandwidth available, the transmission bit rate of new digital speech coding techniques has dropped from 8 Kpbs (CELP), 4.8Kpbs (CS-ACELP) to 2.4 Kbps (MELP,STC). As the bit rate falling, the speech quality can only be maintained by employing very complex algorithms which are difficult to implement in real time.
This thesis investigates a new application specific processor for speech coding processing. The processor is designed to process linear predictive coding and pitch estimation which are the kernels of speech coding techniques. We use hardware-software codesign methodology to optimize the processor architecture and instruction set. The processor use a four-stage pipeline to balance performance and core area. It has two memory banks for vector operation, 24-bit floating-point unit for precision, 8-bit exponent unit for large dynamic range operation and special instructions for parallel operation. Each instruction length is fixed as 16 bits. The instruction set provides 4 special addressing modes and 3-operand operations. This chip can run at 40MHz and the speed is about 4.75 times higher than that of TMS320C30.
The chip is realized by using a TSMC 0.6mu 1P3M CMOS fabrication and synthesis by COMPASS cell library. The silicon area required for the core is approximately 23mm^2. This ASIC has been accepted by the National Science Council Chip Implementation Center (CIC) MPC project for fabrication in Taiwan R.O.C..
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