Study of Low-Temperature Polycrystalline Silicon Thin-Film Transistors

• Main Authors: Tze-Chien Wu, 吳子建
• Other Authors: S. M. Sze
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/11302562395907923993

碩士 === 國立交通大學 === 電子工程系 === 87 === Study of Low-Temperature Polycrystalline Silicon Thin-Film Transistors Student: Tze-Chien Wu Advisor: Prof. S. M. Sze Institute of Electronics National Chiao Tung University Abstract Although the best device and circuit performances have been reported for TFTs fabricated using a high temperature (typically 950。C or above) process, such devices require costly quartz substrates. On the contrary, low temperature technologies (maximum processing temperature 600。C or below) allow cheaper glass substrates to be used. However, the inferior device characteristics may limit the amount and complexity of the peripheral circuits. Recently, several key technologies that have been proposed to improve the performances of low-temperature TFTs and lower the process temperature. In my thesis, we used PECVD TEOS-SiO2 rather than the conventional LPCVD TEOS-SiO2 as the gate insulator. The PECVD TEOS-SiO2 can be deposited at a temperature of 300。C by utilizing plasma assistance. In my thesis, we investigated the performance and reliability of such kind of low-temperature TFTs. We discovered that it could offer adequate performances, such as low leakage current and m=37 cm2/V.s for many display peripheral circuits. We found that the leakage current at low drain voltage exhibited a different mechanism from that of high-temperature TFTs. Besides, after the NH3 plasma treatment, the trap states in the channel were passivated. However, because of worse endurance of high power plasma, many negative fixed oxide charges were trapped in the PECVD TEOS oxide to increase leakage current. On the reliability, we found that there were two types of stress-induced defects, each with a different position within the gate insulator. Stressing under linear regions produced defects across the whole gate insulator, uniformly distributed from the source side to the drain side. Stressing under saturation regions resulted in additional defects near the drain side. This result of the asymmetric behavior is attributed to the presence of hot carriers. In summary, from the results above, we found that the low-temperature TFTs with PECVD TEOS-SiO2 as the gate insulator could provide good performances and reliability. Therefore, it could be a promising method for forming gate insulator of low-temperature poly-Si TFTs.