| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 87 === After CORDIC (Coordinate Rotational Digital Computer) algorithm was presented by Volder in 1959, there were lots of the improved algorithms published. In this thesis, we will first review the basic CORDIC algorithm and structures, and several notable improved algorithms and architecture. We will also point out and analyze the advantages and the disadvantages of those algorithms. In particular, we will focus on the computation of the sine and cosine functions. After the survey, we will present a fast table-based angle encoding method combined with the leading-one bit detection that can greatly speed up the convergence rate of CORDIC algorithm. We also use the pipelined circuit structure to solve the problem of calculating variable scale factor, and speed up the total calculating time. In average, the total iteration number for the rotation and the scale factor compensation is about 4.107 and 3.721, for 22-bit precision. In 0.35μ processor, we get the total circuit area is 20168.75μm2, and the operation period is 7.82ns in typical corner (don't include the delay of ROM). It is to say that it can operation in 127MHz. The thesis is organized as follows. Chapter one is the introduction, including reviews and applications of the well known CORDIC algorithms. Detailed CORDIC algorithms will be introduced in chapter two, including those factors affecting its performance. After that, we will discuss some popular basic techniques for improving performance in chapter three. Their advantages and drawbacks will also be introduced. In chapter four, for solving these problems, we present a fast CORDIC algorithm, which is based on the table-based encoding algorithm, the leading-one bit detection, and the pipelined structure to speed up the total iteration rate. We will details the new CORDIC algorithm and its advantages. We then simulate the algorithms, and list the performance data for comparison and verification in chapter five. Besides, we design our processor by Verilog hardware description language, and optimize it by Synopsys synthesis tool. Then we list the total area and the operation frequency. We use the 0.35μ standard cell to synthesis the circuit. In chapter six, we demonstrate a divider design which uses the similar table-based encoding algorithm and leading-one bit detection to speed up iteration number. At last, we will draw some conclusion and list future work in chapter seven.
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