THE DESIGN AND ANALYSIS OF NEW CMOS IMAGE READOUT INTEGRATED CIRCUIT FOR UNCOOLED INFRARED DETECTOR ARRAY

• Main Authors: Zong-Xin Yu, 余宗欣
• Other Authors: Chung-Yu Wu
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/40339922661432706676

碩士 === 國立交通大學 === 電子工程系 === 87 === The new bolometer IR detector based on the micromachining structure technology has been developed to reduce the cost for commercial applications. The difference between the bolometer and the past photon IR detector is that the bolometer IR detector can operate at a room temperature without an expensive cooling system. But the major disadvantages are the smaller IR sensitivity and the larger background DC signal. Hence the key technique of the IR readout circuits is the elimination of the background DC signal to read out IR signal with minimal distortions. In the past, the readout circuits may be divided into three configurations: Constant Current (CC), Constant Voltage (CV) and Constant Bias (CB). Each of these configurations has its advantages and disadvantages. In this thesis, all of these configurations have been analyzed, designed and taped out. The fabricated chip has been measured. The measurement results also confirm the analysis. Among the three configurations, CC configuration has the most advantages and is used to compose the 64×64 pixels two-dimensional readout circuit. In CC configuration, a transconductor amplifier has been presented to translate the voltage variation caused by the detectors to the current signal, which is used to eliminate the noise in the integration capacitor stage. During the transformation, the linearity of the transconductor amplifier dominates the readout performance. Hence a new transconductor amplifier, named Constant Current Buffered Direct Injection (CCBDI), has been purposed for bolometer IR detectors with a high linearity and a low offset. Further, a current-mode background suppression based on the threshold-voltage compensated current source has been presented to increase the signal dynamic range. A correlated double sampling (CDS) technique has been used to reduce the fixed pattern noise at output stage. A 64×64 pixels two-dimensional readout circuit, which is designed and fabricated by 0.5mm Double-Poly-Double-Metal (DPDM) n-well CMOS technology, has been measured. The measurement results show the uniformity of 81.30%, the linearity of 85.92% and the power dissipation closed to 150mW. In the future, to increase the uniformity, to increase the linearity, and to reduce the power consumption are the important researches.