| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 87 === In this thesis, our goal is to design and optimize new efficient processing cores for 3D graphics. This these is divided into three parts: (I) The datapath design for geometric transformation: First we analysis basic geometric transformation operations used in 3D graphics. Based on the special features of matrix-vector multiplication for geometric transformation, we design a simple architecture that eliminates redundant multiplication. (II) A fused efficient VLSI implementation of radix 2 floating-point arithmetic unit is presented, which is capable of doing division, square root and multiplication. To make the quotient/ root digit's selection function simple, over-redundant radix 2 representation is used. The arithmetic unit complies with IEEE's binary floating-point standard. (III) The datapath design for 3D graphic shading. We introduce some shading methods that are usually used for 3D graphics. A VLSI architecture is designed for Phong shading, which has the best performance for 3D graphics shading. Our targets for this architecture are to decrease the computation of CPU and can arrive the speed's requires for 3D graphics.
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