A NEW STRUCTURE OF CELLULAR NEURAL NETWORKS USING THE NEURON-BIPOLAR JUNCTION TRANSISTOR (vBJT)

• Main Authors: Yeh Chiou-Ling, 葉秋玲
• Other Authors: Wu Chung-Yu
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/68025152770622357084

碩士 === 國立交通大學 === 電子工程系 === 87 === In this thesis, new structures of cellular neural networks designed and fabricated in 0.6μm single-poly-triple-metal (SPTM) n-well CMOS process are presented. The device structure called the neuron-bipolar junction transistor (nBJT) consists of the parasitic PNP bipolar junction transistor and the spreading base resistor array in the CMOS process. To simplify the circuit of the neuron in cellular neural networks, the nBJT is used in the integrated circuit implementation of cellular neural networks, and two circuit designs of the cell are proposed. In the first design, the nBJT is used to implement the neuron and weights of the cell. In the second design, it is used to implement the current summation and weights of the cell, and a diode structure is proposed to realize the neuron. In the two circuit designs of the cell, weights of the cell are realized by the resistance of the resistors in nBJTs. Thus if the spreading resistors are replaced by tunable MOS resistors, the programmable capability is achieved. Compared with previous hardware implementations of cellular neural networks, using the nBJT or the diode structure to realize the neuron not only simplifies the complexity of the circuit, but also makes the layout more compact. Realizing weights by tunable MOS resistors is also a simpler way than previous. Thus high packing density can be achieved. Moreover, weights can be easily tuned by controlling the gate voltages of the MOSs. The functions of the cellular neural networks constructed by the proposed two circuit designs of the cell have been verified by HSPICE simulations, respectively. The first circuit can perform noise removal and the second can be applied in noise removal and shadow detection. The second kind of complete circuits are designed and fabricated in 0.6μm single-poly-triple-metal (SPTM) n-well CMOS process. The chip contains a 16×16 array for noise removal and a 1×5 array for shadow detection. The layout size of each cell is 80×89μm2. Weights of both arrays are programmable, and thus both noise removal and shadow detection can be performed by tuning the weights. Measurement results on the chip also verify that the proposed structure of cellular neural networks can achieve the above two functions.