Hot Carrier Induced Drain Current Degradation in Thin-Oxide n- and p-MOSFET's

• Main Authors: Li-Yuan Huang, 黃立元
• Other Authors: Tahui Wang
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/18702227635735084149

碩士 === 國立交通大學 === 電子工程系 === 87 === Hot carrier induced reliability issues have received considerable interest in deep-submicron CMOSFET's. As device dimension scales down, it's necessary to investigate the geometric dependencies of hot carrier effects, such as gate oxide thickness, gate length, gate width, and isolation technique. In this thesis, three hot carrier reliability issues, drain leakage current degradation in n-MOSFET's and in p-MOSFET's and on-state current degradation in p-MOSFET's, are discussed. First, the mechanisms and characteristics of hot carrier stress induced drain leakage current degradation in thin-oxide n-MOSFET's are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero Vgs such as drain-to-source subthreshold leakage, band-to-band tunneling current and interface trap induced leakage are taken into account. Our result shows that the trap assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, strong oxide thickness dependence of drain leakage degradation is observed; In ultra-thin gate oxide (30Å) n-MOSFET's, drain leakage current degradation is attributed mostly to interface trap creation while in thicker oxide (53Å) devices the drain leakage current exhibits two-stage degradation, a power law degradation in the initial stage due to interface trap generation followed by an accelerated degradation rate in the second stage caused by oxide charge creation. Next, hot carrier effects in p-MOSFET's with various gate lengths and gate widths are investigated. The subthreshold leakage degradation by using STI and LOCOS isolation techniques are compared. It is found that negative oxide charge can enhance subthreshold leakage significantly in short gate length (£ 0.25mm) p-MOSFET's. Moreover, higher electron trapping efficiency at the edge of STI may cause a subthreshold hump and results in a drastic increase of drain leakage current at zero gate bias. This hump effect is not observed in p-MOSFET's with LOCOS isolation. As gate length is further reduced, this hump effect becomes more serious and may impose a limiting factor on the scaling of a p-MOSFET. Finally, on-state drain current degradation in p-MOSFET's due to negative oxide charge, interface trap, and positive oxide charge creation is studied. Negative oxide charge creation can increase on-state drain current while interface trap and positive oxide charge generation causes a reduction of the current. The most serious degradation occurs at a high Vgs bias stress, which decreases the drain current severely.