Design and Analysis of Generic Universal Switch Blocks
碩士 === 國立交通大學 === 資訊科學系 === 87 === A switch block M with W terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of M is at most W) is simultaneously routable through M. In this thesis, we present an...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1999
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/80905779263703106810 |
| Summary: | 碩士 === 國立交通大學 === 資訊科學系 === 87 === A switch block M with W terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of M is at most W) is simultaneously routable through M. In this thesis, we present an algorithm to construct N-sided universal switch blocks with N(N-1)W/2 terminals on each side. Each of our universal switch blocks has N(N-1)W/2 switches and switch-block flexibility N-1. We prove that no switch block with less than W switches can be universal. Further, the decomposition property of a universal switch block provides a key insight into its layout implementation with a smaller silicon area. We also compare our universal switch blocks with others of the topology associated with Xilinx XC4000-type FPGAs. Experimental results demonstrate that our universal switch blocks improve routability at the chip level. Based on extensive experiments, we also explore the interactions between switch-block architectures and routing and provide several suggestions for optimization of the interactions.
|
|---|