| Summary: | 碩士 === 國立交通大學 === 資訊科學系 === 87 === FPGA routing resources consist of wire segments and programmable switches. Routing in FPGAs is performed by programming the switches to make connections between wire segments. The switches usually have high resistance and capacitance, and thus incur significant delays. Researchers have shown that the number of switches, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. In FPGA routing, the number of switches used by a signal is not necessarily proportional to the wirelength of the signal. Therefore, the traditional measure of routing delay based on the geometric distance of a signal is no longer accurate for FPGAs. Further, to improve circuit performance and maintain reasonable routability simultaneously, FPGA routing tracks consist of wires with a versatile set of lengths. Previous work often considers only unit-length wire segments.
In this thesis, we implement an FPGA timing-driven global and detailed router proposed in [41] and present three heuristics to improve the performance of the router. The router considers wire segments of multiple lengths and is based on a timing model associated with the number of switches used. The router uses a hierarchical top-down approach, starting at dividing an entire circuit into two subcircuits by a cut line. At each hierarchical level, we first use a global router to determine the region assignments for connections between the two subcircuits and then apply the weighted bipartite matching algorithm to allocate the detailed routing paths for each net. The hierarchical process proceeds recursively until the subcircuits are easy to be handled. Experimental results show that the timing-driven router can achieve an average of 78\% reduction in the total number of nets violating timing constraints, compared with a router based on the traditional timing model.
We also present three effective heuristics to further improve the performance of the timing-driven router, namely, pin
swapping, bend prediction, and net propagation. The pin-swapping heuristic is to pick a better logic-module pin position to minimize the number of bends used by a net. The bend-prediction heuristic is to predict the number of bends used by a net. The net-propagation heuristic is to assist the detailed router to select more suitable wire segments by propagating the information for net connections. Experimental results show that the pin-swapping, the bend-prediction, and the net-propagation heuristics can achieve respective averages of 41\%, 21\%, and 17\% further reductions in the total number of nets violating timing constraints, compared with the original timing-driven router. Finally, if we simultaneously apply the three heuristics to the original timing-driven router, the total number of timing violations will be reduced by an average of 50\%.
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