Branch Prediction with Associated Register Buffer

碩士 === 國立交通大學 === 資訊工程系 === 87 === Branch instructions are always the performance bottleneck of pipelined superscalar processors by interrupt the steady flow of instruction stream in the pipeline. To resolve this problem, various branch prediction schemes have been proposed. There are 3 b...

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Bibliographic Details
Main Authors: Yu-Chu Li, 李育柱
Other Authors: Chang-Jiu Chen
Format: Others
Language:zh-TW
Published: 1999
Online Access:http://ndltd.ncl.edu.tw/handle/75206349149588317193
Description
Summary:碩士 === 國立交通大學 === 資訊工程系 === 87 === Branch instructions are always the performance bottleneck of pipelined superscalar processors by interrupt the steady flow of instruction stream in the pipeline. To resolve this problem, various branch prediction schemes have been proposed. There are 3 branch prediction schemes are widely used today. The simplest is bimod predictor using 2-bit saturating counts to record the history outcomes of every branch instruction. The 2-level adaptive predictor uses two-level architecture to trace the correlation of nearby branch outcomes. The most complex is the combination predictor, which consists of the bimod and 2-level predictor and use a meta-table to choose which result to be used. To analyze the factors affecting branch instruction outcomes, we find that associated register values take an important role. If we can make reference to the associated register information while making prediction, the accuracy can be improved. In this thesis, we propose a new auxiliary branch prediction mechanism, called as Associate Register Buffer to increase the prediction accuracy of original branch predictors. To implement this mechanism, a 3-entries Instruction Shift Buffer (ISB) is added to find the associated registers of a branch, the BTB entry is extended by adding 4 fields to record the associated register names, and an add-on history buffer to store the correct branch direction. Every time when the original predictor has a wrong prediction, the associated register values and branch address will be hashed to form an index to the history buffer and store the correct outcome. Next time when the branch runs again, the associated register values and branch address will be hashed to index the history buffer and if the entry is valid, the value stored in that entry will be used as our prediction. We simulate our design using the SimpleScalar tools set, and compare with 3 basic predictor models on eight of the SPEC95 benchmarks. The simulation results show that the ARB scheme outperforms all the basic predictor models. Using a 32768 entries of history buffer, the average improvement of accuracy with bimod predictor is 8%. As to 2-level prediction and combination prediction, the average improvements are 7.5% and 3.82% respectively.