Chip Design and Implementation of A New Gray Motion Estimator

• Main Authors: Chung-Ping Chang, 張中平
• Other Authors: Jer-Min Jou
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/70300974137686595536

碩士 === 國立成功大學 === 電機工程學系 === 87 === Video compression is becoming increasingly important with the advent of the multimedium and broadband networks. In the video coding system, the most popular and kernel technique for dynamic video compression is the motion estimation (ME), and the video transmission speed depends on its performance deeply. Due to the temporal and spatial correlation of the image sequence, the motion vector of a block is highly related to the motion vectors of its adjacent blocks in the same image frame. If we can obtain useful and enough information from the adjacent motion vectors, the search times used to find the motion vector of each block may be reduced significantly. In this thesis, we use an efficient gray prediction search (GPS) algorithm .Based on the gray system theory, the GPS can determine the motion vectors of image blocks quickly and correctly. If we want to implement this algorithm as a high performance circuit, we can adopt the pipelined method. Pipelining is a well-known efficient technique for optimally designing high performance digital circuits. However, conventional pipelining techniques are difficult to pipeline the execution of a loop with variant iteration execution lengths in a circuit. So we use a new pipeline design approach, called dynamic pipelining, to design and pipeline the gray motion estimator. We using the 0.6 um of COMPASS standard cell library. The physical layout is generated by using CADENCE CAD tools. The core size (contained pads) is 7072.8 ×7018.8um2 and the gate count is about 3274. By the simulation, it can process an image which divide into 352 piels × 288 lines blocks with a clock rate of 66 MHz in real time.