| Summary: | 碩士 === 國立成功大學 === 資訊工程研究所 === 87 === In this thesis, the computation requirements of 3D graphics and virtual reality are analyzed. According to the computation requirements, some existing architectures of multimedia hardware, for example, the Microsoft Talisman and NSC98 microprocessor, are compared. Obviously, their capability can not sufficiently support 3D graphics computations. To satisfy the computation requirements of 3D multimedia applications, we propose an architecture of highly integrated media processor which is extended from the micro-architecture of NSC98. This architecture consists of a RISC core and some special functional units. In this architecture, most multimedia operations are performed on a Multimedia Functional Unit (MFU), which is Intel MMX compatible. But, to speed up the performance of multimedia computation, we develop another five new instructions to be included into the Intel MMX compatible instruction set. Besides, a CORDIC unit responsible for executing the instructions with long latency is also developed. In this thesis, we focus on the circuit design of CORIDC unit that calculates the triangular functions.
In the design of CORDIC unit, we propose three novel ideas to obtain an excellent solution. First, we modify the double rotation CORDIC algorithm to work on 360-degree full rotation range. It is important for supporting image-based VR computations in a high-performance manner. Second, to enhance performance and reduce circuit cost, the scheme of packed-formatted I/O is adopted. Third, an on-line number translation scheme is applied to reduce number translation time.
In this thesis, the CORDIC unit is modeled by Verilog language, and the COMPASS 0.35μm cell library and Synopsys EDA tool are adopted to synthesize the CORDIC circuit. Until now, we have accomplished logic circuit thesis and timing simulation takes of the CORDIC unit. Then, it will be delivered to Chip Implementation Center at National Science Council for IC prototyping.
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