Design and Implementation of a Low-Power Subranging Analog-to-Digital Converter
碩士 === 國立中興大學 === 電機工程學系 === 87 === This thesis describes the design of an 8-bit low-power CMOS subranging analog-to-digital converter. The dynamic latch-type comparators with zero static power consumption are used to implement the high-speed low-power A/D converter. The DAC uses an optim...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/27827560200306138946 |