Controlling ATPG To Improve Testability Problem Caused By Multiple-Branch

• Main Authors: LIEN CHIA CHUN, 連家駿
• Other Authors: 王行健 老師
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/96209898483845471964

碩士 === 國立中興大學 === 資訊科學研究所 === 87 === Abstract With the increase in the complexity of VLSI circuitry, the issues of testing and design-for-testability (DFT) are becoming increasingly important. Considering testability during the early stages of the design flow can have many benefits, including significantly improved fault coverage, reduced test hardware overhead, and reduced design iteration times. In this paper, We present a method that modifies the original behavioral code to deal with the testability problems caused by conditional case statement under Built-In Self-Test (BIST) environment. We will develop solutions for the problems under high-level design environment.