| Summary: | 碩士 === 義守大學 === 資訊工程學系 === 87 === Recently, the development of the multimedia system and the prevailing of the Internet have making a great deal of data flood with the network such as text, image, and video etc. In accordance with the correctness of data during transmission or receiving and reducing the needed of space stored, there has been several well-development algorithms solved about those problems. For instance, the Image Compression System and the Reed-Solomon Coding System are the famous in those fields. And how to develop such hardware system has become a trend of system designing in the future.
For the sake of those purposes, this thesis presents a subject about the implementation of the Test Bench for image compression and Coding by using programmable logic devices such as FPGAs. We have promote the traditional design methodology and combined a new design concept called Codesign in developing the whole Test Bench using FPGAs. The Test Bench is designed for image compression and coding, therefore, we must have an overall understanding of the image compression and RS Coding system. So, on the purpose of ensuring the practicable of the Test Bench, the simulation of the algorithms and emulation of the hardware modules of the whole processing are necessary. And according to the current developing of the Test Bench, the prototyping system will build easily. We can confirm that the practicable of the Test Bench and less time needed for transferring the algorithms into the hardware modules.
In this thesis, we have finished the image compression system by using the Codesign concept under support of the Test Bench, to test the functionality of the Test Bench. The related results have presented in the chapter 7.
This method, on the experience, will be suited for developing the RS Coding system. And the results also indicated that they achieve a significant improvement on the developing of the whole system.
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