Optimal Design and Yield Consideration for SOI Devices

• Main Authors: Bou Yung Yang, 楊步雲
• Other Authors: Yang, Ping-Chang
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/42857540057282124228

碩士 === 逢甲大學 === 電機工程學系 === 87 === The research mainly deals with the yield enhancement of silicon- on-insulator (SOI) MOSFETs from optimal design. The anomalous ID -VGfS and ID -VDS characteristics in a floating body fully depleted silicon-on-insulator (SOI) nMOSFET with parasitic bipolar junction transistor (BJT) is also analyzed. All current components in the MOSFET as well as parasitic BJT are considered in this analysis. It shows that the single-transistor latch in ID -VGfS characteristics is due to multistable floating body potentials. The study also reveals that the breakdown and latch phenomena are strongly dependent on the parasitic bipolar current gain and multiplication factor. By using previously developed physical models for the bulk and SOI MOSFETs, we examine design considerations to exploit the unique benefits of VLSI circuit manufacturability in thin-film SOI MOSFET. We compare and analyze the statistical variation of the threshold voltage in both the bulk and SOI MOSFETs with respect to variation of device parameters such as doping concentration, oxide thickness, channel length etc. In general, our study reveals that the threshold voltage of fully depleted thin-film SOI MOSFET's is less sensitive to the variation of device parameters, and hence may result in an improved yield over their bulk silicon counterpart.