| Summary: | 碩士 === 逢甲大學 === 自動控制工程學系 === 87 === According to software & hardware simulation based on ART1, this thesis implemented these hardware circuits through CPLD supported by Altera and finished this ART1 chip design and verification about recalling part. The weighting values are from learning part in the Artificial Neural Network chip. The character is a two-value (0 and 1) input vector with 5*5 matrix. Under different vigilance parameters with and without noise input, we do the hardware simulation and testing. Joining 4 kinds of noise patterns with random choice and refers to standard patterns input, these circuits in vigilance value of 0.85 have good ability of anti-noise. Besides, we use two kinds of the bit maps as input patterns to verify these circuits and the results are correct. It shows that these circuits also can be used to cluster the bit maps. The software package is Max+Plus II and the hardware is FLEX EPF10K50RC240-3 which are produced by Altera Corp. We use AT89C51 to send out patterns as inputs of the ART1 chip. The testing result is correct and its operating frequency can achieve 20MHz. So far, the recalling part has combined the learning part into a neural network chip programmed in CPLD and can do on-line learning and recalling. By using Cadence software package, we have finished the design of the neural network chip and passed the evaluation of the Chip Implement Center. It will be fabricated in the process of T06-88B.
|
|---|
