| Summary: | 碩士 === 中華大學 === 電機工程學系碩士班 === 87 === Memory evolution is an indicator of the overall semiconductor industry. The process and performance improvement directly challenges the technician to their objectives. This thesis aims to point out the challenges of the architecture and technic of the next generation semiconductor memories(NGSM's).
In this thesis, the architecture and operation of the next generation semiconductor memories is introduced firstly. Then it is to compare their performance and applications. And this will let us know how many problems as likes EMI, EMC and length etc. about the operation of memory in the high-frequency.
Furthermore, it is arised that difficulty to verify the next generation semiconductor memories due to the poor tester performance. The product specification will effect the production quality. If the test condition and tester spec. are poor, the cost will be increased and the quality will be lost.
The NGSM's performance and architecture has the better design than the one of conventional standard memories. Consideration of the application, the technic and the economics, next generation semiconductor memories are the only way to improve the performance on bandwidth. The two memories of PC-133 SDRAM and DDR SDRAM will be the market mainstream for the next two years. The Direct RDRAM have the cost problem presently. When their cost is down, the next memory mainstream will be the Direct RDRAM.
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