Chip Design and Implementation of ATM/AAL5 Reassembly Processor with Hashing Searching Technique

• Main Authors: Yu-Cheng Gong, 龔育正
• Other Authors: Kim-Joan Chen
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/02418171915322587520

碩士 === 國立中正大學 === 電機工程研究所 === 87 === Today, as the demand of network bandwidth keeps growing, ATM technology is being considered as a suitable platform. Many R&D organizations and network companies have invested the research on developing the ATM NIC for the PC host. In these few years, we have developed several versions of ATM NIC for the PC. We have also devoted our efforts on the development of next generation ATM NIC. This new version of the ATM NIC improves the performance significantly. We extend such performance to handle 128 connections simultaneously. Furthermore, we have included the ABR traffic management function to this ATM NIC. Due to these changes, the architecture becomes more complicated, and therefore makes the system more practical. In this thesis, we first introduce the new version of the ATM NIC, then we describe the Reassembly Processor. We explain our design consideration in details. Considerations include the environment that the Reassembly Processor is formed. We discuss the reassembly functions and structure used by some other high performance ATM NICs. We adopt the Xilinx XC4000 series FPGA chips. The design flow is based on the Top-Down approach. First, we decide what are the specifications required for the chip. We write the FSM and associated modules by using Verilog HDL. We use the Synopsis FPGA Express to synthesize our codes. We use the Xilinx tool to convert and PAR (Place and Route) the circuit, and then download the design into FPGA chip to do the tests. Finally, we design a test board to verify our designed FPGA. We have successfully realized this implementation.