Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times
碩士 === 元智大學 === 電資與資訊工程研究所 === 86 === For the high speed VLSI design, timing budget is often very tight and more accurate timing analysis is required. This demands more accurate method for timing characterization of library cells. One approach to increasing the accuracy is to consider sim...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/61568051171515770837 |