Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times

碩士 === 元智大學 === 電資與資訊工程研究所 === 86 === For the high speed VLSI design, timing budget is often very tight and more accurate timing analysis is required. This demands more accurate method for timing characterization of library cells. One approach to increasing the accuracy is to consider sim...

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Main Authors:	Hui-Hsiang Tung, 董慧香
Other Authors:	Rung-Bin Lin
Format:	Others
Language:	en_US
Online Access:	http://ndltd.ncl.edu.tw/handle/61568051171515770837

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spelling	ndltd-TW-086YZU003920782015-10-13T17:34:50Z http://ndltd.ncl.edu.tw/handle/61568051171515770837 Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times 不同到達時間的多元輸入訊號覆疊之元件時序特性化 Hui-Hsiang Tung 董慧香碩士元智大學電資與資訊工程研究所 86 For the high speed VLSI design, timing budget is often very tight and more accurate timing analysis is required. This demands more accurate method for timing characterization of library cells. One approach to increasing the accuracy is to consider simultaneously all the inputs that will influence the output response. In this thesis we propose an approach to timing characterization of a multi-input gate. The approach would consider input slopes, output load and arrival times of all the inputs that influence the output response. A preliminary multiple-delay logic simulator is designed based on the proposed approach. The timing delay produced by the multiple-delay logic simulator is within ±10% of that obtained by HSPICE simulation. Rung-Bin Lin 林榮彬學位論文 ; thesis 54 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 元智大學 === 電資與資訊工程研究所 === 86 === For the high speed VLSI design, timing budget is often very tight and more accurate timing analysis is required. This demands more accurate method for timing characterization of library cells. One approach to increasing the accuracy is to consider simultaneously all the inputs that will influence the output response. In this thesis we propose an approach to timing characterization of a multi-input gate. The approach would consider input slopes, output load and arrival times of all the inputs that influence the output response. A preliminary multiple-delay logic simulator is designed based on the proposed approach. The timing delay produced by the multiple-delay logic simulator is within ±10% of that obtained by HSPICE simulation.
author2	Rung-Bin Lin
author_facet	Rung-Bin Lin Hui-Hsiang Tung 董慧香
author	Hui-Hsiang Tung 董慧香
spellingShingle	Hui-Hsiang Tung 董慧香 Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times
author_sort	Hui-Hsiang Tung
title	Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times
title_short	Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times
title_full	Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times
title_fullStr	Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times
title_full_unstemmed	Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times
title_sort	timing characterization of gate delay with multiple input transitions of different arrival times
url	http://ndltd.ncl.edu.tw/handle/61568051171515770837
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Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times

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