Timing Characterization of Gate Delay with Multiple Input Transitions of Different Arrival Times
碩士 === 元智大學 === 電資與資訊工程研究所 === 86 === For the high speed VLSI design, timing budget is often very tight and more accurate timing analysis is required. This demands more accurate method for timing characterization of library cells. One approach to increasing the accuracy is to consider sim...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/61568051171515770837 |
| Summary: | 碩士 === 元智大學 === 電資與資訊工程研究所 === 86 === For the high speed VLSI design, timing budget is often very tight and more accurate timing analysis is required. This demands more accurate method for timing characterization of library cells. One approach to increasing the accuracy is to consider simultaneously all the inputs that will influence the output response. In this thesis we propose an approach to timing characterization of a multi-input gate. The approach would consider input slopes, output load and arrival times of all the inputs that influence the output response. A preliminary multiple-delay logic simulator is designed based on the proposed approach. The timing delay produced by the multiple-delay logic simulator is within ±10% of that obtained by HSPICE simulation.
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