AC-3 EXPONENT DECODING AND BIT ALLOCATION PROCESS CHIP DESIGN AND IMPLEMENTATION
碩士 === 大同工學院 === 電機工程研究所 === 86 === AC-3 is the perceptual coding tecnology and needed a lot of computation. In AC-3, the exponent decoding and bit allocation process which the values are 16 bits is one of the most computation and is implemented by a simple CPU architecture. The simple CP...
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| Format: | Others |
| Language: | zh-TW |
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1998
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00202689337969639877 |
| Summary: | 碩士 === 大同工學院 === 電機工程研究所 === 86 === AC-3 is the perceptual coding tecnology and needed a lot of computation. In AC-3, the exponent decoding and bit allocation process which the values are 16 bits is one of the most computation and is implemented by a simple CPU architecture. The simple CPU can do all the computing in the AC-3 decoder except the IMDCT for no multiplicatives in the CPU. In this CPU, the multiplicative is replaced by the shifter and adder to implement.The CHIP is implememted by TSMC 0.6 um SPTM technolog and the maximum frequency of this circuit is 125 MHz. The layout area of this chip is 5832*5832 um.
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