Low-Power CMOS Continuous-Time Filter Design

• Main Authors: Huang Cheng-Chang, 黃成昌
• Other Authors: Jan Yaw-Fu
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/46848689851680571071

碩士 === 大同工學院 === 電機工程研究所 === 86 === Design considerations for low-power continuous-time current-mode filters are presented in the thesis. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and a MOSFET gate capacitance. Integrator excess phase shift is reduced by using balanced signals path, and open-loop gain is increased by using low-voltage cascode amplifiers. Replacing the ideal current source with temperature-independent current bias generator, the unity gain of the integrator will not vary with process and temperature. Consequently, the filter need not be tuned. The lowpass prototypes provided 100KHz-2MHz tunable bandwidth. For ladder filters derived from doubly terminated LC prototypes, HSPICE simulations predict a -3dB bandwidth of 470 KHz for a fifth-order Butterworth low-pass filter. Power dissipation is 17.6 uW/pole with 1.6 V power supply.