Power Analysis and Power-Driven Synthesis for VLSI Systems

• Main Authors: Yuan, Shih-Yi, 袁世一
• Other Authors: Sy-Yen Kuo
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/17996972034541922294

博士 === 國立臺灣大學 === 電機工程學系 === 86 === Research on analysis and synthesis for low power VLSI system has been performed in this thesis. A new static power analysis method for CMOS combinational circuits is first presented. This approach integrates the simulation-based method and the probabilistic method together, and can establish the relationships between the primary inputs and the internal nodes in the circuit. Based on the relationships, our approach can also indicate which internal node or input sequence consumes the most power. It is thus suitable for performing power estimation in the synthesis environment for power optimization. Furthermore, by using the existing piecewise linear delay model as well as the proposed algorithm and the partitioning methods, this novel method is also very accurate and efficient. For a set of benchmark circuits, the experimental results show that the power estimated by our technique is within 5% error as compared with that by the exact SPICE simulation, while the execution speed is more than four orders of magnitude faster. For the sake of generality, the characteristic of logical operations of the new proposed method must be justified to suit for all digital circuits. Thus, we present theoretical foundation of the new static power estimation method for CMOS combinational circuits. This analysis can show how the operators work and obey the logic law on node level. We then present a new global routing algorithm for low power. This approach is based on the new symbolic power analyzer proposed. Thus, the power analyzer can provide enough information to focus and identify the "hot-spots", the parts that consume significant power or generate many glitches. The new routing algorithm then uses this information to improve the circuit routing. It is thus suitable for power optimization in the synthesis environment. For a set of benchmark circuits, the experimental results show that our technique decreases the power-area product by 5%-15%.