| Summary: | 碩士 === 國立臺灣大學 === 電機工程學系研究所 === 86 === System designers are facing a rapidly growing system complexity with system-on
-a-chip (SOC) going to come true. A multimillion-gate chip design using a trad
itional ASIC approach would take years instead of months to develop. To accele
rate pace of system development, system designers intend to integrate intellec
tual properties (IP) into the chip. Such IP in chip design industry refers to
pre-designed pre-verified building blocks that can be reused for faster time-t
o-market. In this thesis, we propose the design methodologies for IP creation
and integration. First we choose the FIR filter as the target design and creat
e one tap of the filter as a hard IP. To make the IP a reusable block and IP-b
ased design more efficiently, higher-level abstractions are created. Then we i
ntegrate FIR filters by parallel and serial method. Two 8-tap parallel FIR fil
ters with different aspect ratios and a serial FIR filter are created in use o
f the tap we have designed. The chip design schedule will be
shortened for the run time and number of iteration times being
reduced. Besides, the chip designed successfully by the IP-
based method has expected performance. Thus it can be seen that
the design methodology can really make efficient design of
large chips and the performance of the chips is quite reliable.
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