| Summary: | 博士 === 國立臺灣大學 === 電機工程學系研究所 === 86 === VLSI circuits with millions of transistors are now common, conventional
logic-level and physical-level design tools cannot deal with the increasing
complexity of VLSI circuit design without the participation of partitioning.
Especially, in submicron designs, interconnection delays tend to dominate
gate delays; therefore, the partitioning problem which concerns on dividing a
circuit into partitions of components to minimize the number of
interconnections
between partitions becomes more and more important.
In this Dissertation, we focus our efforts on developing a set of robust tools
for partitioning VLSI circuits subject to the size constraints and with min-cut
as its objective. Three partitioners are included in this set
of tools: a single
-level (i.e., non-clustering based) Module_Migration_Partitioner (MMP), a Two_
Level_Partitioner (TLP), and a Multi_Level_Partitioner (MLP).
To!begin with, we propose a single-level partitioner MMP based on the iterative
improvement technique. This partitioner implicitly promotes the move of an
entire cluster into one partition during the module migration process by paying
more attention to the neighbors of moved modules, relaxing the size constraints
temporarily during the migration process, and controlling the module migration
direction. Moreover, MMP adopts a self- adjusted probabilistic function set to
reduce the sensitivity of some important parameters. As shown
in the experiments,
the solution quality and, most important, the unstable property of FM-type
partitioners resulting from partitioning a circuit with different deviations
from the exact bipartition can be improved by MMP.
As problem size grows larger, the performance of a non-clustering based
partitioner tends to degrade. To remedy, clustering based partitioners have to
be used. Therefore, we also propose a two-level partitioner TLP
which integrates
MMP with an efficient clustering algorithm. The clustering algorithm is the
combination of a bottom-up clustering technique for module/
cluster merging and a
top-down recursive clustering technique. Then, MMP is used as a partitioner in
the two-level scheme. Experimental results show that TLP exhibits superiority
over other two-level partitioners.
The above two-level partitioner TLP can be easily extended to a multi-level
partitioner MLP. Since a multi-level partitioner performs multiple clustering
and partitioning processes, this will give the partitioner more opportunities
to refine the obtained solutions. According to the experiments, the multi-level
partitioner MLP generates high-quality solutions with promising runtime
performance, especially for cases of large-size circuits.
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