Design and Analysis of Channel-Hot-Hole-Induced-Hot-Electron Injection Programming in P-Channel Flash Memory

• Main Authors: Wang, Yen-Sen, 王彥森
• Other Authors: Hsu, Ching-Hsiang
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/63776129216176475921

碩士 === 國立清華大學 === 電機工程研究所 === 86 === 　　P-channel Flash memory has advatanges of low voltage operation, low power consumption, better scalability and hot-hole injection free, but disadvantages of small rdad current and serious drain disturbance at the same time. For p-channel Flash operation optimization, we have to design programming scheme, threshold voltage window and programming condition properly to balance the merit and the drawbacks. 　　The conventional channel-hot-hole-induced-hot-electron injection is not a reliable programming scheme under threshold voltage dispersion of erase state for p-channel Flash mermory. To improve programming reliability and speed, a constant current programming by ramp-up stair-case gate pulse is proposed. By using the constant current programming, a high speed, self-convergence and possible multi-level operation without verification can be implemented. Meanwhile, different start voltages and ramp rates of ramping-up gate pulse patterm lead to distinct convergent ability and programming speed respectively. Therefore, the "rogramming Observations Program" development is necessary for programming optimization.This program is based on gate current spectrum extraction by programming chain and coupling ratio extraction by subthreshold slope technique. The programming characteristics, gate current during programming, trajectory of gate current, drain disturbance characteristics, threshold voltage distribution of programming/erase state and drain current during programming are generated after arbitrary gate pulse pattern input. For p-channel Flash operation optimization, threshold voltage window has to be designed first by considering read current and drain disturbance by means of POP. After that, the programming can be achieved by certain ramp ratesof gate pulse pattern for both normal bit and degraded bit, and the fastest programming condition is also present. As a result, the p-channel Flash memory operation optimization can be implemented by meas of constant current programming scheme and gate pulse pattern estimation. However, if the result is not good enough, re-design or other approaches, for example drain engineering etc. should be proceeded.