| Summary: | 碩士 === 國立清華大學 === 工業工程研究所 === 86 === For semiconductor manufacturing industries, high manufacturing costs are coupled with numerous, complex manufacturing processes and strict manufacturing environment. Since any yield loss will induce huge increase of manufacturing costs, the semiconductor manufacturing companies are always searching for methods to enhance the yield of their products. Besides in-line process control, off-line failure analysis is another important approach to improve the yield of semiconductor products.
In this research, an engineering-data based semiconductor failure analysis system is presented. The goal of this system is to clarify the relationship between circuit probe yield and defects, via the comparison between Bin map and various defect maps gathered from in-line inspection, such that the contribution of various manufacturing processes to the failure of chips can be traced.
Through the experiments conducted in a semiconductor company, it can be proven that the failrue analysis system developed in this research possesses the capability of finding our the root cause of yidle loss. By the assistance of this system, engineers can more effectively find out process problems to achieve the goal of yield improvement and enhancement.
|
|---|
