Layout-based Logic Decomposition for Timing Optimization
碩士 === 國立清華大學 === 資訊工程學系 === 86 === As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes dominated by the interconnect delay. In a traditional top-down design flow, logic synthesis algorithms optimize gate area...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1998
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| Online Access: | http://ndltd.ncl.edu.tw/handle/55933639489736422574 |