Performance-Driven Placement and Routing Refinement for Virtual- Wire-Based Hardware Emulation

• Main Authors: Wei, Shuan-Shien, 魏選賢
• Other Authors: Youn-Long Lin
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/98475322893146882960

碩士 === 國立清華大學 === 資訊工程學系 === 86 === A hardware emulator consists of multiple FPGAs interconnected to emulatethe given design circuit. The biggest problem with hardware emulator is that the logic utilization for each FPGA is rather low due to the fact thatpin count provided by current FPGA packaging technology can not keep the samepace as the logic capacity, so the logic utilization is limited by the pin count, which leads to the so-called Pin-Limitation problem. Virtual- Wire technology overcomes Pin-Limitation by multiplexing multiplelogical wires over a physical wire in a Time-Division- Multiplexing fashion.The architecture is to parallelly output signals from certain FPGA toa group of shift registers and drive these signals one at a time serially to a physical wire connecting neighboring FPGAs, then neighboring FPGAs convert those serial input signals to parallel input signals byanother set of shift registers.We propose, in the thesis, a system that combine a proper way of scheduling signals, which is termed Phase-Assignment, with routing and placement refinement to minimize the emulation cycle time.