Power Characterization and Estimation Using Polynomial Simulation for CMOS Circuit
碩士 === 國立交通大學 === 電子工程研究所 === 86 === In this thesis, we present a method to estimate the power consumption for a designed CMOS circuit. During the characterization, we calculate transition energy E01 and E10 of each node. Then, we use zero delay logic simulation and the node transition energy...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1998
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/24810766489666805047 |