| Summary: | 博士 === 國立交通大學 === 電子工程學系 === 86 === In this thesis the BJT-based silicon retinas and their
applications onimage edge extraction and moving object detection
are designed and analyzed.The main parts of this thesis include:
(1) the characterization and analysis ofimage smoothing
functions in the BJT-based silicon retina; (2) theimplementation
of the new BJT-based silicon retina using tunable imagesmoothing
capability; (3) the implementation of the new image edge
extractor using BJT-based silicon retina and thresholding
detector; (4) the design of thenew motion sensor with BJT-based
silicon retina and temporal zero-crossing detector.Firstly, the
analytical models of the smoothing function of the BJT-based
silicon retina under both single-point and multiple-point
stimuli havebeen developed by considering the base resistance
bias effect of the common-base BJT array. Through the
analytical models, the operatingprinciple of the image smoothing
performed by the BJT smoothing network of the BJT-based silicon
retina can be well understood. Moreover, theparameters which
affect the image smoothing characteristics of the BJT-
basedsilicon retina can be characterized by the developed models
and suitabledesign guidelines can be obtained. It may be seen
from the derived equations that the smoothing characteristics
depend upon the image contrast andbackground, which makes the
BJT-based silicon retina adaptive in imagesmoothing.
Experimental chip has been designed and fabricated by 0.6 um
CMOS technology. Both measurement results and SPICE simulation
results have substantiated the developed analytical model and
verified the performance advantages of the BJT-based silicon
retina. Thus the model can be used to efficiently simulate
large-size BJT-based silicon retina which cannot be simulated in
SPICE.Secondly, an improved BJT-based silicon retina with simple
and compact structure is proposed and analyzed. In the proposed
structure, the BJT smoothing network which models the layer of
horizontal cells in the vertebrate retina is implemented by
placing enhancement n-channel MOSFETs among the bases of
parasitic BJTs existing in CMOS process toform an unique and
compact structure. The nMOSFET can be operated in subthreshold
region or strong-inversion region to provide a wide-range
tunable channel resistance controlled by the common gate bias.
Thus the smoothing characteristics can be tuned in a wide range.
Moreover, an extra emitter isincorporated with each BJT at the
pixel to act as the row switch. This reducesthe cell area of
the silicon retina and increases the resolution. Using the
proposed new structure, an experimental 64*64 BJT-based silicon
retina chip has been fabricated by using 0.5um CMOS technology.
The measurement results on the tunability of the smooth area in
the smoothing network as well asthe dynamic characteristics of
the proposed silicon retina in detecting moving objects have
been presented. It is believed that theimproved structure is
verysuitable for the VLSI implementation of the retina and its
application systemsCMOS smart sensors.Thirdly, a compact and
real-time 2-D edge sensor integrated with the embedded DRAM is
proposed and analyzed. In the proposed edge sensor, the
computation algorithm is based upon the algorithm inspired by
the biologicalmodel of detecting spatial edges by thresholding
the outputs of the siliconretina. Each basic detection cell in
the sensor has a compact architecture which consists of one BJT-
based silicon retina cell, one thresholding edge detector, and a
DRAM storage cell. The significant features of the edge sensor
are that the image acquisition and edge image generation can be
performed in a parallel manner, and the DRAM storage cell can be
incorporated into eachcell without additional interface circuits
to store the resultant edge image forfurther processing by
following processing system, such as neural network.Using the
proposed architecture, an experimental 128*128 edge sensor
chipwith a cell size of 30*30 um2 has been designed by using
0.25 um DRAM technology. The correct operations of the designed
sensor chip have been verified through simulations. The
complete sensor consumes about 150 mW at 3.3V.Finally, a 2-D
velocity- and direction-selective visual motion sensorwith BJT-
based silicon retina and temporal zero-crossing detector is
proposed and implemented. In the proposed sensor, the modified
token-based delay-and-correlate computational algorithm is
adopted to detect the specified speed and direction of moving
object images. Moreover, binary pulsed signals areused as
correlative signals to increase the velocity and direction
selectivities. Each basic detection cell in the sensor has a
compact architecture which consists of one BJT-based silicon
retina cell, one current-input edge extractor, two delay paths,
and four correlators.Using the proposed architecture, an
experimental 32*32 visual motion sensor chip with a cell size of
100*100 mm2 has been designed and fabricatedby using 0.6 mm CMOS
technology. The correct operations of the fabricatedsensor chip
have been verified through measurements. The measured rangesof
selectively detected on-chip velocity and direction in the
fabricated sensor chip are 56mm/sec~5m/sec (1120pixel/sec~105
pixel/sec) and 0 degree ~360 degree, respectively. The complete
sensor consumes 20mW at 5V.From the above results, it is
believed that the proposed BJT-basedsilicon retina and its
application architectures on edge extraction and motiondetection
have a great potential in system-on-a-chip design of machine
visionsystems which mimic human vision to achieve various
efficient imageprocessing. Further researches in this field
will be conducted in the future.
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