Design, Performance Evaluation, and Fault Diagnosis of a Distributed Knockout ATM Switching System

博士 === 國立交通大學 === 電子工程學系 === 86 === In this dissertation, a nonblocking ATM switch module with input andoutput buffer for constructing a very large scale ATM switching networkis proposed. The maximum size of the proposed ATM switch module is limitedto K x...

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Main Authors: Cheng, Yuh-Jiuh, 鄭玉鉅
Other Authors: Lee Tsern-Huei, Shen Wen-Zen
Format: Others
Language:zh-TW
Published: 1998
Online Access:http://ndltd.ncl.edu.tw/handle/51650736363890962222
id ndltd-TW-086NCTU0428008
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spelling ndltd-TW-086NCTU04280082015-10-13T11:06:15Z http://ndltd.ncl.edu.tw/handle/51650736363890962222 Design, Performance Evaluation, and Fault Diagnosis of a Distributed Knockout ATM Switching System 分散式擊倒非同步傳送模式交換系統之設計、性能評估及錯誤診斷 Cheng, Yuh-Jiuh 鄭玉鉅 博士 國立交通大學 電子工程學系 86 In this dissertation, a nonblocking ATM switch module with input andoutput buffer for constructing a very large scale ATM switching networkis proposed. The maximum size of the proposed ATM switch module is limitedto K x K where K=(CL x 8)/(L+1) and CL and L denote the cell length and thenumber of links per output port, respectively. If CL = 64 octets and L = 3,the size of the proposed ATM switch module can be up to 128 input-output ports.Using this ATM switch module, a 16,384 x 16,384 ATM switching network can beobtained based on the three-stage Clos- type interconnection. The proposed ATMswitch module can be implemented by three types of fully customer VLSI chips.With a little modification, the proposed switch can provide multicast services.A three-stage multicast switching network is also designed. Furthermore,multicast routing algorithms such as call setup and call release proceduresare presented for our proposed switching network. The proposed ATM switch module is a modified version of an existingdistributed-knockout-switch. In the proposed ATM switch module, an input portwith a nonempty queue always sends a cell to the switch at the beginning ofeach time slot. The cell sent out from an input port reaches either itsdestination output port (if it wins the contention) or a different input port(if it loses). A priority scheme is adopted to preserve service-cell sequencing.A cell is discarded if it loses a predetermined number of consecutive contentions. Simulations are performed to evaluate the proposed ATM switch module underboth uniform and hot-spot nonuniform traffic models. For achieving fault tolerance, we present an efficient fault diagnosisprocedure to detect, locate, and identify the fault type of single switchelement faults for the switch element array of the distributed-knockout-switch.The proposed fault diagnosis procedure can also be used in the diagnosis ofthe proposed ATM switch module. To facilitate fault diagnosis, the operationof switch elements is slightly modified. Our diagnosis procedure can locatemost single switch element faults in two phases. Faults which cannot belocated in two phases can always be located in a third phase. Binary searchalgorithms are developed to locate some kinds of single switch element faultsin the third phase.ATM peripheral modules play an important rule in ATM systems. In this dissertation,a CAM-based header translation and traffic control chip is designed for theATM header translation, and traffic policing and gathering for every VPI/VCI.This chip can be used in the implementations of user network interface (UNI)and network network interface (NNI) for ATM systems. Besides, a trafficcontrollable cell assembler and disassembler chip is designed for implementationof a CPN in future B-ISDN applications. Lee Tsern-Huei, Shen Wen-Zen 李程輝, 沈文仁 1998 學位論文 ; thesis 109 zh-TW
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language zh-TW
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description 博士 === 國立交通大學 === 電子工程學系 === 86 === In this dissertation, a nonblocking ATM switch module with input andoutput buffer for constructing a very large scale ATM switching networkis proposed. The maximum size of the proposed ATM switch module is limitedto K x K where K=(CL x 8)/(L+1) and CL and L denote the cell length and thenumber of links per output port, respectively. If CL = 64 octets and L = 3,the size of the proposed ATM switch module can be up to 128 input-output ports.Using this ATM switch module, a 16,384 x 16,384 ATM switching network can beobtained based on the three-stage Clos- type interconnection. The proposed ATMswitch module can be implemented by three types of fully customer VLSI chips.With a little modification, the proposed switch can provide multicast services.A three-stage multicast switching network is also designed. Furthermore,multicast routing algorithms such as call setup and call release proceduresare presented for our proposed switching network. The proposed ATM switch module is a modified version of an existingdistributed-knockout-switch. In the proposed ATM switch module, an input portwith a nonempty queue always sends a cell to the switch at the beginning ofeach time slot. The cell sent out from an input port reaches either itsdestination output port (if it wins the contention) or a different input port(if it loses). A priority scheme is adopted to preserve service-cell sequencing.A cell is discarded if it loses a predetermined number of consecutive contentions. Simulations are performed to evaluate the proposed ATM switch module underboth uniform and hot-spot nonuniform traffic models. For achieving fault tolerance, we present an efficient fault diagnosisprocedure to detect, locate, and identify the fault type of single switchelement faults for the switch element array of the distributed-knockout-switch.The proposed fault diagnosis procedure can also be used in the diagnosis ofthe proposed ATM switch module. To facilitate fault diagnosis, the operationof switch elements is slightly modified. Our diagnosis procedure can locatemost single switch element faults in two phases. Faults which cannot belocated in two phases can always be located in a third phase. Binary searchalgorithms are developed to locate some kinds of single switch element faultsin the third phase.ATM peripheral modules play an important rule in ATM systems. In this dissertation,a CAM-based header translation and traffic control chip is designed for theATM header translation, and traffic policing and gathering for every VPI/VCI.This chip can be used in the implementations of user network interface (UNI)and network network interface (NNI) for ATM systems. Besides, a trafficcontrollable cell assembler and disassembler chip is designed for implementationof a CPN in future B-ISDN applications.
author2 Lee Tsern-Huei, Shen Wen-Zen
author_facet Lee Tsern-Huei, Shen Wen-Zen
Cheng, Yuh-Jiuh
鄭玉鉅
author Cheng, Yuh-Jiuh
鄭玉鉅
spellingShingle Cheng, Yuh-Jiuh
鄭玉鉅
Design, Performance Evaluation, and Fault Diagnosis of a Distributed Knockout ATM Switching System
author_sort Cheng, Yuh-Jiuh
title Design, Performance Evaluation, and Fault Diagnosis of a Distributed Knockout ATM Switching System
title_short Design, Performance Evaluation, and Fault Diagnosis of a Distributed Knockout ATM Switching System
title_full Design, Performance Evaluation, and Fault Diagnosis of a Distributed Knockout ATM Switching System
title_fullStr Design, Performance Evaluation, and Fault Diagnosis of a Distributed Knockout ATM Switching System
title_full_unstemmed Design, Performance Evaluation, and Fault Diagnosis of a Distributed Knockout ATM Switching System
title_sort design, performance evaluation, and fault diagnosis of a distributed knockout atm switching system
publishDate 1998
url http://ndltd.ncl.edu.tw/handle/51650736363890962222
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