The design and implementation of the ALU of the SA-110 microprocessor

• Main Authors: Wang, Leng Feng, 王蘭豐
• Other Authors: Wu Chuan-Lin
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/08871341976637031701

碩士 === 國立交通大學 === 資訊工程學系 === 86 === This thesis discusses the organization of the ALU of the SA-110microprocessor and we describe the organization in hardware des-cription language. We construct the ALU by analyzing the micro-operations of the data processing instructions in SA-110 micro-processor instruction set. SA-110 microprocessor is a pipelined RISC CPU, there are five stages in the pipeline. There are threebasic functional units we have constructed in the ALU: arithmeticlogical operation unit, shift unit and multiply unit. The exe-cution of the shift instructions is in the shift unit; the execution of the multiply instructions is in the multiply unit and the execution of the arithmetic and logical instructions isin the arithmetic logical operation unit. This thesis includes the detail introduction of the organization of the functional units and we describe them in Verilog(R) HDL. These programs were integrated with the control unit of the SA-110 micro-processor also.