Analysis of Error Reduction Algorithms for Pipelined A/D Converters
碩士 === 國立成功大學 === 電機工程學系 === 86 === In this thesis, linearity analysis, capactior-mismatch error reduction algoritgms,and digital correction algorithms for pipelined analog-to-digital converters are presented. The error sources which limit...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1998
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| Online Access: | http://ndltd.ncl.edu.tw/handle/68605852954713996053 |