A 16/18/20-bit input-format Sigma-Delta D/A Converter for Digital Audio Application

• Main Authors: Shih, Ko-Yan, 施克彥
• Other Authors: Kuo Tai-Haur
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/01972394490844873235

碩士 === 國立成功大學 === 電機工程學系 === 86 === For digital-to-analog (D/A) converter design, resolution higher than 16-bit has never been achieved in Taiwan. In this thesis, a stereo sigma-delta D/A conversion with 16/18/20-bit input-format has been successfully implemented. This D/A converter is composed of a 64X upsampling digital interpolator, a fifth order sigma-delta digital modulator, and an off-chip analog interface circuit. To reduce the area cost and relax the operational complexity, a 3-stage interpolator is proposed. The first and the second internal stage of the interpolator are designed as a half-band FIR lowpass filter, and the third stage is designed as a sinc filter. Besides, the operational complexity of the 3-stage interpolator could be reduced to one-eighth of that of a single-stage one. Moreover, a fifth-order multiple-feedback sigma-delta modulator (SDM) is used, and an instability recovery mechanism, which uses a technique called internal linear feedback (ILF), is applied to this SDM. This D/A converter is implemented in an FPGA and also designed as an ASIC. In the design using FPGA, an Altera's FLEX10k70 FPGA demo-board is used and is connected to a commercial compact disk player for exhibition. In the ASIC design, Opus cell library with TSMC 0.6 um single-poly triple-metal CMOS technology is used. Active area of the chip is about 5.29 mm2. Total gate count numbers is about 15,900 (without RAM and ROM). Finally, the measured results are reported. With 16-bit resolution input, dynamic range (DR) of 92.1dB can be achieved. With 18-bit and 20-bit resolution input, DR of 101.2dB and 109.1dB can be achieved, respectively. Besides, measured harmonics are all below -110dB.