Design and Implementation of A Scalable Pipeplined Architecture for 2-D Discrete Wavelet Transform

• Main Authors: Liang, Ming-Shiang, 梁閔翔
• Other Authors: Jou Jer-Min
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/89124829623093768323

碩士 === 國立成功大學 === 電機工程學系 === 86 === The Discrete Wavelet Transform (DWT) is a newly developed signal processing method and it has proven to be much useful for a wide rangeof applications including signal analysis, compression, pattern recognition,biomedicine, and numerical analysis, etc. Especially in future image/videocompression standards, the discrete wavelet transform is a likely candidatefor the transform part of them. Therefore, the design and implementationof an efficient signal processing architecture which can perform thesetransforms has itself taken on much importance. In this thesis, a scalable pipelined architecture for computing separable2-D Discrete Wavelet Transform is presented. The architecture is regular andmodular for computation of 2-D DWT. Based on these properties, it is easilyscalable for different filter lengths and different decomposition levelswithout complex control. In addition, the architecture has the characteristicsof lower hardware cost, shorter latency, and higher throughput, it is suitablefor VLSI implementation and for real-time applications. Since the multipliers are the critical paths in the architecture, we designtwo-stage pipelined multipliers to increase the operating speed. Finally, weuse the hierarchical modular design technique for our architecture by CAD toolsand the circuit has been simulated and verified by Altera MAX+PLUS II. From thesimulation results, the circuit has a working frequency of 17MHz.