Test Vector Compaction for Multiple Circuits
碩士 === 國立成功大學 === 電機工程學系 === 86 === Single scan chain architectures suffer from long test application time,while multiple scan chain architectures require large pin overhead and arenot supported by Boundary Scan. In this paper, we present a...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/16725714127432206167 |