| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 86 === Single scan chain architectures suffer from long test
application time,while multiple scan chain architectures require
large pin overhead and arenot supported by Boundary Scan. In
this paper, we present a novel method toallow a single input
line to support multiple scan chains. By appropriatelyconnecting
the inputs of all circuits under test during ATPG process
suchthat the generated test patterns can be broadcast to all
scan chains whenactual testing is executed, we show that 177 and
280 patterns are enough todetect all detectable faults in all 10
ISCAS'85 combinational circuits and10 largest ISCAS'89
sequential circuits, respectively.Index Terms- design for
testability, test generation, scan based design,Boundary Scan
(IEEE 1149.1) and test compaction.
|
|---|
