A 2-D Non-separable DWT Parallel Architecture Based on MPRA Algorithm
碩士 === 國立成功大學 === 電機工程學系 === 86 ===
Main Authors: | Peng, J. Y., 彭振亞 |
---|---|
Other Authors: | Ho Y. K. |
Format: | Others |
Language: | zh-TW |
Published: |
1998
|
Online Access: | http://ndltd.ncl.edu.tw/handle/37523801050400658163 |
Similar Items
-
Dual Priority Scheduling Algorithm Used in the nMPRA Microcontrollers – Dynamic Scheduler
by: Lucian ANDRIEȘ, et al.
Published: (2015-06-01) -
2-D DWT system architecture for image compression
by: Ang, Boon Hui
Published: (2012) -
The Events Priority in the nMPRA and Consumption of Resources Analysis on the FPGA
by: CIOBANU, E.-E.
Published: (2018-02-01) -
An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications
by: Vasile Gheorghiță Găitan, et al.
Published: (2021-06-01) -
An Efficient Lifitng Based Architecture for 2-D DWT Used in JPEG2000
by: Hung-Ying Chen, et al.
Published: (2003)