VLSI Design of an ATM Switch Controller with Multicast Functions
碩士 === 國立中興大學 === 電機工程學系 === 86 === Multimedia application over the internet needs a large bandwidth andwell managed network architecture. Asynchronous transfer mode (ATM),the state of the art network technology, provides both requirements....
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1998
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83376922337928680348 |
| Summary: | 碩士 === 國立中興大學 === 電機工程學系 === 86 === Multimedia application over the internet needs a large bandwidth
andwell managed network architecture. Asynchronous transfer mode
(ATM),the state of the art network technology, provides both
requirements.One key component of the ATM network is the ATM
switch. In this thesis, a novel ATM switch architecture based on
the shared multibuffer structure is proposed. It incorporates a
cyclic address queue algorithm and can support up to 622 Mb/s
transmission rate. Hardware cost is reduced while throughput is
elevated by using the proposed architecture.An dynamic multicast
scheme along with the multicast queues method isintroduced to
handle multicast applications. The unfairness problemcaused by
adopting the multicast queue is improved. In this thesis,the
VLSI design of the switch controller is also described. The
gate-levelcircuit derived with the help of CAD tools amd Compass
standard celllibraryusing 0.6 um single poly three metal CMOS
technology. The gate-levelcircuit can work at 60 MHz under the
intrinsic delay model.
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