A Study on AC Characteristics of 0.18um gate length PMOSFET

• Main Authors: Lee, Da-Yuan, 李達元
• Other Authors: Shyh-Chyi Wong
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/51285823632962228902

碩士 === 逢甲大學 === 電機工程研究所 === 86 === In high density VLSI circuit scaled, MOS device scaling down has led to reliability problems, such as off-sate leakage current and hot carrier degradation. All of these problems need to be resolved in the next generation device development. Halo structure is usually adopted in deep submicron MOS devices for off-state leakage current reduction. Tilt angle of the Halo implant determines dopant distribution which gives anti-punch through operation. In this paper, we investigate the impact of tilt angle on both DC and AC performance of Halo PMOS device via 2-D simulations. For DC performance, it is found that same conduction current is obtained for all tilt angles at same leakage current level. This performance equivalence can be traced back to a self compensation between body factor and source resistance, and implies that low tilt angle should be adopted for Halo devices, as it gives small threshold voltage and thus high noise margin. For AC performance, it is found that at same leakage current level, all tilt angles give same gate- to-drain capacitance and that lower tilt angle gives smaller drain-to-bulk junction capacitance.