| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 86 === In this thesis, we study two important problems arising in VLSI physical design, which are circuit partitioning and floorplanning. For circuit partitioning, the multi-way ratio-cut circuit partitioning problem is addressed, and five efficient spectral algorithms are presented. The common key idea of the first three algorithms is to add a preprocessing step, which effectively groups the vertices into clusters, into one of the currently best spectral algorithms called MELO+DP-RP. The experiment results show that all of the three algorithms can reduce the run time of MELO+DP-RP while maintaining comparable partitioning results. As for the fourth and fifth algorithms, their common key idea is to first treat all the vertices as a cluster, and then repeatedly select a cluster, which gives the maximum cost improvement after being partitioned, and partition it into two new clusters. The bi-partitioning process is continued until the number of clusters equals the number of partitions. The experimental results indicate that the last two algorithm generate much better partitioning results in much less run time than MELO+DP-RP. For floorplanning, the floorplanning problem with routability considerations is formulated, and a new routability-driven floorplanner is presented. The key idea of the new floorplanner is to measure the chip routability in terms of the utilization of each soft block. Based on the idea, the floorplanner is designed by combining the binary search technique and a modified version of the well-known simulated annealing based floorplanner. The experimental results are provided to demonstrate the effectiveness of the new floorplanner.
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