A New Approach for Technology Mapping Based on Node Equations

• Main Authors: Chen Yung-Fu, 陳永福
• Other Authors: Hsieh Tsai-Ming
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/61360424478980148450

碩士 === 中原大學 === 資訊工程研究所 === 86 === In this thesis, we proposed a new technology mapping algorithm for seque-ntial circuits. The proposed algorithm tries to minimize the clock period, the number of LUTs, and the number of registers simultaneously. Construct to the existed algorithms, the mapping solution of the proposed algorithm, depends only on the function of the circuit, not on the initial realization.This new algorithm can be divided into four steps as follow:1. Transforming the initial circuit into the logic equations which are called node equations.2. Reducing the number of the node equations by merging two or more node equ- ations. In this step, the operations of retiming and replication are perf- ormed.3. Performing the combinational technology mapping algorithm, e.g. FlowSYN ..., etc, with logic resynthesis on the circuits for depth minimization.4. Retiming the mapped circuits for further delay-time optimization.In step3, if we decompose sub-circuits so that some common parts of circuits can be extracted, the area of the resulting solution can be further reduced. According to the experimental results, the delay time, the number of LUTs andFFs all are less 4%, 39%, 75% than the result of TurboMap algorithm, respect-ively.