Design of a Low-Power VLSI Cell Library Exploiting Different Types of CMOS Logic Circuits

• Main Authors: Huang, Po-Shin, 黃柏勳
• Other Authors: Jinn-Shyan Wang
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/61109740573820096504

碩士 === 國立中正大學 === 電機工程學系 === 86 === A cell library which can be used to design a low-power VLSI is proposed. lsoThe usage of this cell library is compatible with the existent EDA mm CMOSenvironment.m the post-layout simulation, the power reduction ration of theThe features of the proposed cell library include:1. Three kinds of logic style, i. e. Complementary CMOS logic, Pass-Transistor Logic and Pass- Transistor/Complementary Mixed CMOS Logic, are used in the design of cells. Which logic style for each cell is selected is based on the consideration to achieve the best performance.2. The NAND/NOR/OAI cells adopt the Complementary CMOS logic and the MUX/XOR/XNOR cells are composed of the Pass-Transistor Logic. Additionally, Pass-Transistor/ Complementary Mixed CMOS Logic is applied to design new- function cells those rarely appear in the conventional cell library.3. The new cells that adopt the Pass-Transistor/ Complementary Mixed CMOS Logic have better performance than the cells with the same function but adopting Complementary CMOS Logic or Pass-Transistor logic. The reason is that the transistor sizing is considered in advance to achieve better performance.4. No matter which logic style is exploited, the output of each cell is designed to have a full swing, which can avoid the problem due to the feedback mechanism in the LEAN cell. The mechanism of the feedback PMOS will induce more gate delay and power consumption.5. The total number of different functions in the new cell library is increased. Then, the power consumption of a VLSI design using this cell library is proved to be lower.6. The function complexity of some new cells is properly raised. If the same function is implemented through conventional standard cells, it will require several small cells to accomplish. Thus, a given application may require less gate count when using the new cell library. By the way, the total interconnection length will also be shortened, and the power consumption can be further reduced. This property is important for deep-sub- micron VLSI designs.The MCNC Logic Synthesis 91 benchmark circuits are designed by using the newly developed cell library. It is found that the chip area, interconnectionlength and power consumption are significantly reduced. The power reductionratio is 14% on average and maximum reduction ration can be up to 34%,comparing to designs using the conventional cell library.A 4-bit ALU is alsoimplemented and fabricated using the proposed cell library in a 0.6mm CMOSprocess. From the post-layout simulation, the power reduction ration of thedesign utilizing the new cell library is up to 43% as compared with thatdesigned with the conventional cell library.