Performance Study of a Shared Buffer ATM Switch

• Main Authors: Sheu, Jeng-Shin, 許正欣
• Other Authors: Dou, Chie
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/81393418452202497541

碩士 === 國立雲林科技大學 === 電機工程技術研究所 === 85 === This master thesis is concerned with the performance study in a shared buffer switches during congestion which have been intensively studies in recent years in order to meet the grade of service required by a wide variety of B-ISDN services. It is commonly required that an overall congestion control strategy within the ATM switches can provide "fair" access to the network resources for all user. According as "fair", this thesis classifies the buffer management schemes into two different bases: Per port basis and the overall basis. For the per port basis, at which the control policies applied to the incoming cells during the congestion are according to the conditions of their associated output queues, a "gated" cell discarding policy is proposed. That is by adding a control gate in front of the logical queue pertaining to each overloaded output port, some incorning cells destined for the overloaded ports can be blocked. So making rooms in the shared buffer for accommodating incoming cells destined for the non-overloaded ports. This scheme for per port basis can not only satisfy the "fair" access requirement under network congestion, but also can reduce the total number of discarded cells. For the overall basis, at which control policies applied to incoming cells are according to the conditions of the overall output queues in a shared buffer switch, a theoretic proving of the optimal buffer management is present. The criteria of this optimality is to make the queues as long as possible, except the longest queue. In addition, the characterization of an ATM shared buffer switch under imbalance traffic conditions is also investigated in the thesis.