An Efficient Viterbi Decoder with Reduced Power Dissipation and Its VLSI Implementation

• Main Authors: Ju, Wann-Shyang, 朱萬庠
• Other Authors: Shieh, Ming-Der
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/47146318444406232806

碩士 === 國立雲林科技大學 === 電子與資訊工程技術研究所 === 85 === 　　The Viterbi algorithm (VA), widely used in digital communication, is known to be an efficient method for the realization of maximum likelihood decoding of convolutional codes. It can also be viewed as a dynamic search problem to find the shortest path. However, the computational complexity of the Viterbi decoder (VD) will be exponentially dependent on the memory order of the convolutional code such that the hardware complexity and its corresponding power dissipation will be also increased. That is why the VD is not suitable for applications of convolution encoding with high memory order. 　　In recent years, there has been tremendous interest in implementing highspeed Viterbi decoders which usually result in massive hardware size and larger power dissipation. In general, the hardware size can be greatly reduced by means of VLSI technology. However, as the increasing demands for portability, as well as concerns about heat dissipation and reliability, low-power design has become a critically important issue in many practical applications such as digital cellular and portable systems. In this thesis, an efficient VLSI architecture for the Viterbi decoder based on the modified T-algorithm is developed for reducting average power dissipation. At the meantime, the inplace computation is used to reduce the hardware requirement for the path metric memory management. 　　From the modified radix-2 butterfly module, on the average, only 16 states at each time stage are needed to be processed for the (4,1,6) convolutional code at bit error probability Pb=10-5 based on the software simulation compared with 64 states in the conventional VD. Therefore, significant power reduction can be achieved by reducing the total number of metric computation and eliminationg waste memory read/write operations. In the thesis, we also model the memory management of the in-place computation as a covering problem such that alsternatiove memory structures can bc easily developed to avoid the use of ping-pong mode memory and to speed up the memory access time. Finally, an implementation of the VD is accomplished by using the 0.6um SPDM process based on the COMPASS cell library for the (4,1,6) Viterbi decoder.