| Summary: | 碩士 === 大同大學 === 電機工程研究所 === 85 ===
A design of a 10-tap linear phase finite-impulse response filter using redundant number representations is presented in the thesis. In this design, the inputs and outputs are represented in two's complement binary fomi and the internal numbers are represented in radix-2 redundant digit form. This redundant result is then converted to two's complement binary form by using the proposed fast parallel conversion scheme. The use of a redundant number system leads to fast carry-free addition, where the cany propagates only through two stages, independent of the word length. Thus, the FIR filter can operate at very high frequency. However, this design trades off area with time and needs more area.
To realize this circuit in a single chip, we use the CADENCE tools and the cell library, COMPASS06 (0.6μm single-poly, double-metal CMOS technology), to implement it. The gate count of tills filter is about 17596 gates. The operating clock can be speeded up to lOOMHz.
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